JPS6156543B2 - - Google Patents

Info

Publication number
JPS6156543B2
JPS6156543B2 JP4528482A JP4528482A JPS6156543B2 JP S6156543 B2 JPS6156543 B2 JP S6156543B2 JP 4528482 A JP4528482 A JP 4528482A JP 4528482 A JP4528482 A JP 4528482A JP S6156543 B2 JPS6156543 B2 JP S6156543B2
Authority
JP
Japan
Prior art keywords
central processing
sub
processing unit
signal
bus
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
JP4528482A
Other languages
English (en)
Japanese (ja)
Other versions
JPS58163031A (ja
Inventor
Masataka Imai
Shigefumi Ikeda
Kyoshi Takezawa
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Omron Corp
Original Assignee
Omron Tateisi Electronics Co
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Omron Tateisi Electronics Co filed Critical Omron Tateisi Electronics Co
Priority to JP4528482A priority Critical patent/JPS58163031A/ja
Publication of JPS58163031A publication Critical patent/JPS58163031A/ja
Publication of JPS6156543B2 publication Critical patent/JPS6156543B2/ja
Granted legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/36—Handling requests for interconnection or transfer for access to common bus or bus system
    • G06F13/362—Handling requests for interconnection or transfer for access to common bus or bus system with centralised access control
    • G06F13/3625—Handling requests for interconnection or transfer for access to common bus or bus system with centralised access control using a time dependent access

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Multi Processors (AREA)
  • Bus Control (AREA)
JP4528482A 1982-03-20 1982-03-20 バス割当制御方式 Granted JPS58163031A (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP4528482A JPS58163031A (ja) 1982-03-20 1982-03-20 バス割当制御方式

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP4528482A JPS58163031A (ja) 1982-03-20 1982-03-20 バス割当制御方式

Publications (2)

Publication Number Publication Date
JPS58163031A JPS58163031A (ja) 1983-09-27
JPS6156543B2 true JPS6156543B2 (en]) 1986-12-03

Family

ID=12715005

Family Applications (1)

Application Number Title Priority Date Filing Date
JP4528482A Granted JPS58163031A (ja) 1982-03-20 1982-03-20 バス割当制御方式

Country Status (1)

Country Link
JP (1) JPS58163031A (en])

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6174049A (ja) * 1984-09-19 1986-04-16 Hitachi Ltd 要求選択方式
JPS6278604A (ja) * 1985-10-02 1987-04-10 Hitachi Ltd プロセス入出力回路共有化装置
US4777487A (en) * 1986-07-30 1988-10-11 The University Of Toronto Innovations Foundation Deterministic access protocol local area network

Also Published As

Publication number Publication date
JPS58163031A (ja) 1983-09-27

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